Overview

The demand for high-speed wireless and communication applications has pushed the development of SiGe and SiGeC epitaxial base HBT processes [1]. The corresponding circuit design activities essentially depend on accurate compact models of SiGe HBTs in all relevant modes of the transistor operation. Unlike the high-performance digital CMOS that can afford a few years between products, the analog and mixed-signal applications involving SiGe demands significantly reduced product cycle time. Thus, there is an intimate relationship between the TCAD, process development and circuit designers.

For many advanced high-speed and RF circuits, the impact of substrate parasitic elements on bipolar transistor electrical performances cannot be neglected. These parasitic elements influence strongly the output characteristics. A compact model consists of lumped elements such as resistors, diodes, capacitors and dependent current sources connected together with minimum number of nodes to form an equivalent circuit to represent a semiconductor device. All lumped elements can be calculated directly from layout and technological data. Development of reliable device models is an essential part in the circuit design for analog and mixed-signal applications. Accurate device characterisation also plays an important and critical role in model development and circuit benchmarking.

The combination of narrow basewidth, due to epitaxial growth techniques, has resulted in a tremendous performance boost of SiGe-based bipolar transistors. In order to capture the resulting new electrical and physical effects occurring in such technologies, improved compact models are needed for predicting accurately the circuit performance. A compact model should incorporate all physics relevant to future technology...