TABLE OF CONTENTS A system-on-chip (SoC) can integrate a large number of components such as microcontrollers, digital signal processors (DSPs), memories, custom hardware and reconfigurable hardware in the form of field programmable gate arrays (FPGAs) together with analogue-to-digital (A/D) and digital-to-analogue (D/A) converters on a single chip (Figure 5.1). The communication structures become ever more sophisticated consisting of several connected and segmented buses or even packet switched networks. In total there may be dozens or hundreds of such components on a single SoC. These architectures offer an enormous potential but they are heterogeneous and tremendously complex. This also applies to embedded software. Moreover, the overall system complexity grows faster than system size due to the component interaction. In fact, intra-system communication is becoming the dominant factor for design, validation and performance analysis. Consequently, issues of communication, synchronisation and concurrency must play a prominent role in all system design models and languages.
The design process for SoCs is complex and sophisticated. From abstract models for requirements definition and system specification more and more refined models are derived leading eventually to low level implementation models that describe the layout and the assembler code. Most of the models are generated and processed either fully automatically or with tool support. Once created models have to be verified to check their consistency and correctness.
Figure 5.2 depicts a few of the models typically generated and transformed during a design project. Different design tasks require different models.
