TABLE OF CONTENTS Shrinking process technologies and increasing design sizes have led to billion-transistor integrated circuits (ICs). To reduce IC design and manufacturing costs, test development and test application must be quick as well as effective. High transistor counts in ICs result in large test data sets, long test development and application times and the need for expensive test equipment. Effective test development techniques that enhance the utilisation of test data, testing time and test equipment are therefore necessary to increase production capacity and reduce test cost.
Test resource partitioning (TRP) deals with the partitioning and optimisation of test resources to enhance test effectiveness and reduce test cost. This chapter describes the use of TRP for complex ICs and presents recent advancements in test access mechanisms, test scheduling and test data compression.
This chapter begins with an introduction to the latest IC design philosophy system-on-a-chip (SoC). Increasing SoC sizes leadto greater test resource requirements for manufacturing test. This growth in test resource requirements motivates the need for efficient TRP techniques during SoC test development.
SoCs are craftedby system designers who purchase intellectual property (IP) circuits, known as embedded cores, from core vendors and integrate them into large designs. Embedded-cores are complex, pre-designed and...
