TABLE OF CONTENTS Increasing integration densities made possible by shrinking device geometries will have to be fully exploited to meet the computational requirements of applications in domains such as multimedia processing, automotive, ambient intelligence. For instance, the computational load of typical ambient intelligence tasks will be ranging from 10 MOPS for lightweight audio processing, 3 GOPS for video processing, 20 GOPS for multilingual conversation interfaces and up to 1 TOPS for synthetic video generation. These workloads will have to be delivered with tightly constrained power levels (from a few watts, for wall-plugged appliances, to a few milliwatts, for portable and wearable devices), affordable cost and high reliability [1]. System architecture and design technology must adapt to the critical challenges posed by both the large-scale integration and the small features of elementary devices.
To tackle the application and integration complexity challenges, and the ensuing design productivity gap, SoCs are and will increasingly be designed by re-using large-scale programmable components, such as microprocessors, micro-controllers and media-processors, as well as large embedded memory macros and numerous standard peripherals and specialised co-processors. Design methodologies have to support component re-use in a plug-and-play fashion in order to be effective. In this reuse-dominated context, there is little doubt on the fact that the most critical factor in system integration will be the scalability of the communication fabric among components. This conclusion is further strengthened if we focus on...
