Digital Systems Design with FPGAs and CPLDs

In the past, digital circuits were designed by hand on paper using techniques such as Boolean expressions, circuit schematics, Karnaugh maps, and state transition diagrams. With the increasing use of computer-based design methods and tools, the design process migrated to the computer using electronic design automation (EDA) tools [1]. These are computer-aided design (CAD) tools developed to support the designers of electronic hardware and software systems. Circuit schematic design entry, supported with design simulation tools, became the design entry and validation (through simulation) method available. With the subsequent development and standardization of hardware description languages (HDL), the HDL design entry method using text-based descriptions of circuits is now often the preferred choice of designers [2 4]. HDL design is supported with simulation, as with circuit schematic design entry, and with logic synthesis (normally referred to simply as synthesis), which converts (synthesizes) the HDL design description into a circuit netlist consisting of the required logic gates and interconnection wiring [5, 6]. Many EDA tools also provide a means by which to view the HDL code as a circuit schematic, thereby providing a graphical view of the design hardware. Such graphical views can aid the designer in understanding the circuit operation and for design debugging purposes.
This chapter provides an introduction to design with HDLs, with particular emphasis on the VHDL language. As such, all examples in this chapter and this text book are provided in VHDL.
Hardware description language (HDL) design entry is based on the...