TABLE OF CONTENTS In order to write VHDL code efficiently, it is essential to know what data types are allowed, and how to specify and use them. In this chapter, all fundamental data types are described, with special emphasis on those that are synthesizable. Discussions on data compatibility and data conversion are also included.
VHDL contains a series of pre-defined data types, specified through the IEEE 1076 and IEEE 1164 standards. More specifically, such data type definitions can be found in the following packages / libraries:
Package standard of library std: Defines BIT, BOOLEAN, INTEGER, and REAL data types.
Package std_logic_1164 of library ieee: Defines STD_LOGIC and STD_ULOGIC data types.
Package std_logic_arith of library ieee: Defines SIGNED and UNSIGNED data types, plus several data conversion functions, like conv_integer(p), conv_unsigned(p, b), conv_signed(p, b), and conv_std_logic_vector(p, b).
Packages std_logic_signed and std_logic_unsigned of library ieee: Contain functions that allow operations with STD_LOGIC_VECTOR data to be performed as if the data were of type SIGNED or UNSIGNED, respectively.
All pre-defined data types (specified in the packages/libraries listed above) are described below.
BIT (and BIT_VECTOR): 2-level logic ( 0 , 1 ).
Examples:
SIGNAL x: BIT;-- x is declared as a one-digit signal of type BIT.SIGNAL y: BIT_VECTOR (3 DOWNTO 0);-- y is a 4-bit vector, with the leftmost bit being the MSB.SIGNAL w: BIT_VECTOR (0 TO 7);-- w is an 8-bit vector, with the rightmost bit being the MSB.
Based on the...
