TABLE OF CONTENTS Finite state machines (FSM) constitute a special modeling technique for sequential logic circuits. Such a model can be very helpful in the design of certain types of systems, particularly those whose tasks form a well-defined sequence (digital controllers, for example). We start the chapter by reviewing fundamental concepts related to FSM. We then introduce corresponding VHDL coding techniques, followed by complete design examples.
Figure 8.1 shows the block diagram of a single-phase state machine. As indicated in the figure, the lower section contains the sequential logic (flip-flops), while the upper section contains the combinational logic.
The combinational (upper) section has two inputs, being one pr_state (present state) and the other the external input proper. It has also two outputs, nx_state (next state) and the external output proper.
The sequential (lower) section has three inputs (clock, reset, and nx_state), and one output (pr_state). Since all flip-flops are in this part of the system, clock and reset must be connected to it.
If the output of the machine depends not only on the present state but also on the current input, then it is called a Mealy machine. Otherwise, if it depends only on the current state, it is called a Moore machine. Examples of both will be shown later.
The separation of the circuit into two sections (figure 8.1) allows the design to be broken into two parts as well. From a VHDL perspective, it is clear that the lower part, being...
