TABLE OF CONTENTS The purpose of this chapter, along with the preceding chapters, is to lay the basic foundations of VHDL, so in the next chapter we can start dealing with actual circuit designs. It is indeed impossible or little productive, at least to write any code efficiently without undertaking first the sacrifice of understanding data types, operators, and attributes well.
Operators and attributes constitute a relatively long list of general VHDL constructs, which are often examined only sparsely. We have collected them together in a specific chapter in order to provide a complete and more consistent view.
At the end of the chapter, a few design examples will be presented. However, due to the fact that this is still a "foundation" chapter, the examples are merely illustrative, like those in the preceding chapters. As mentioned above, we will start dealing with actual designs in chapter 5.
VHDL provides several kinds of pre-defined operators:
Assignment operators
Logical operators
Arithmetic operators
Relational operators
Shift operators
Concatenation operators
Each of these categories is described below.
Are used to assign values to signals, variables, and constants. They are:
<= Used to assign a value to a SIGNAL.
:= Used to assign a value to a VARIABLE, CONSTANT, or GENERIC. Used also for establishing initial values.
=> Used to assign values to individual vector elements or with OTHERS.
Example: Consider the following signal and variable declarations:
SIGNAL x : STD_LOGIC;VARIABLE y : STD_LOGIC_VECTOR(3 DOWNTO 0); -- Leftmost bit is MSB<a name="114"></a><a...
