TABLE OF CONTENTS Having finished laying out the basic foundations of VHDL (chapters 1 to 4), we can now concentrate on the design (code) itself.
VHDL code can be concurrent (parallel) or sequential. The former will be studied in this chapter, while the latter will be seen in chapter 6. This division is very important, for it allows a better understanding of which statements are intended for each kind of code, as well as the consequences of using one or the other.
The concurrent statements in VHDL are WHEN and GENERATE. Besides them, assignments using only operators (AND, NOT, +, *, sll, etc.) can also be used to construct concurrent code. Finally, a special kind of assignment, called BLOCK, can also be employed in this kind of code.
We start this chapter by reviewing the fundamental differences between combinational logic and sequential logic, and by contrasting them with the differences between concurrent code and sequential code.
By definition, combinational logic is that in which the output of the circuit depends solely on the current inputs (figure 5.1(a)). It is then clear that, in principle, the system requires no memory and can be implemented using conventional logic gates.
In contrast, sequential logic is defined as that in which the output does depend on previous inputs (figure 5.1(b)). Therefore, storage elements are required, which are connected to the combinational logic...
