TABLE OF CONTENTS Where a calculator on the ENIAC is equipped with 18,000 vacuum tubes and weighs 30 tons, computers in the future may have only 1,000 vacuum tubes and perhaps weigh 1.5 tons.
Popular Mechanics, March 1949
This Chapter describes the packet buffer architecture and design used in the Intel Internet Exchange Architecture (Intel IXA) Portability Framework. It addresses the following questions:
What is the representation of a packet in the Intel IXA Portability Framework?
What is the format of the various data structures associated with a packet?
How does you allocate and free a packet?
How are large packets or jumbo frames handled?
What is the support available for handling multi-cast packets?
What is the packet buffer API available in the Intel IXA Portability Framework?
High performance packet forwarding requires a highly optimized packet buffer architecture that allows applications to allocate, free, access, and modify packet buffers efficiently. The chapter highlights some of the optimizations built into the architecture and design that is used by the Intel IXA Portability Framework.
The representation of a packet is a fundamental design concept and is critical for understanding any networking application. Packet representation has three elements. First, you need to specify how and where the packet data is stored. Second, you need a format for state information that is associated with the packet, such as packet size, type of packet, offset of valid data in the packet, and so forth. Finally, you need a unique...
