TABLE OF CONTENTS If we really understand the problem, the answer will come out of it, because the answer is not separate from the problem.
J. Krishnamurti
This chapter describes the packet movement model used on the data plane by the the Intel Internet Exchange Architecture (Intel IXA) Portability Framework. The chapter begins by presenting a high-level logical view of the fast-path packet-processing tasks in a typical networking application. It then maps this view to the hardware elements on an Intel IXP2XXX network processor. It explains in detail specific features of the software architecture and the associated design tradeoffs to help you understand the rationale for the chosen model. These tradeoffs include the use of a run-to-completion model for the packet-processing tasks, use of parallelism versus pipelining, processing packets from DRAM rather than directly from RBUF elements, processing on End of Packet (EOP) versus Start of Packet (SOP), and so on.
Finally, the chapter walks through the packet flow in a sample packet-processing thread. Using the example, it highlights the implementation of the data flow graph by the dispatch loop, state sharing between microblocks, and design optimizations such as packet header and descriptor caching.
Figure 5.1 shows a high-level logical view of the fast-path processing in a typical networking application. The application receives and processes packets from one or more network media interfaces. The packet-processing tasks may include flow classification, policing, header checks, look-ups for forwarding the packet, header encapsulation/decapsulation, and...
