TABLE OF CONTENTS Let me take you a button-hole lower.
Shakespeare
Every packet-processing pipeline starts with a microblock that receives packets from a media interface and ends with one that writes packets to a media interface. This chapter provides a high-level overview of the design for these microblocks.
The Intel IXA network processor SDK includes microblocks for receiving and transmitting packets on different media interface types. These microblocks are thoroughly tested, and if they meet your requirements, you can save considerable time by simply including them in your application. If for any reason you need to modify these microblocks or write your own, then this chapter can help you understand the associated design concepts and challenges. The chapter also describes the Media Switch Fabric (MSF) hardware briefly. More details are available in the hardware reference manuals for each of the Intel IXP2XXX Network Processors. In addition, the Intel Internet Exchange Architecture (Intel IXA) Software Building Blocks Developers Manual (Intel 2004g) describes the low-level data structures and interfaces for these microblocks.
Chapter 2 introduces the MSF unit, which interfaces IXP2XXX network processors to MAC/PHY devices. The MSF provides a consistent receive and transmit interface to the microengines and isolates them from the details of the media device.
The MSF buffers packets and cells coming in from a media interface in fixed-size segments called Receive Buffer or RBUF elements. The RBUF elements are part of an 8-kilobyte RAM in the MSF. This 8-kilobyte...
