TABLE OF CONTENTS The large-signal equivalent circuit will be introduced in four steps. First, the basic topologies for an ideal intrinsic BJT describing the DC behavior are addressed. Then, the the parasitic and nonideal DC currents are added, and the location of the capacitances is motivated. Finally, the different ways to account for transit-time effects are discussed. Since we discuss here merely the equivalent-circuit topology as the basis of the model, the HBT electrical characteristics are only addressed where necessary to motivate the inclusion of specific elements or to explain their impact on the electrical performance in general.
For bipolar transistors, both T- and hybrid- ?-topology equivalent circuits are in use. While the small-signal behavior usually is described in T-topology, large-signal models commonly are based on the ?-topology.
The choice in the case of the small-signal model is usually driven by the close link between T-topology and device physics. On the other hand, the large-signal model topology is determined by tradition the Ebers-Moll and Gummel-Poon models rely on the ?-topology since it is slightly simpler and has a more intuitive link to DC measurements. However, the question how to transform one topology into the other is not only a philosophical one. Nonlinear models often are derived from various small-signal models determined at different bias conditions, therefore one has to transform the parameters from one description into the other. It is also a question of whether the...
