TABLE OF CONTENTS Frank Ghenassia and Alain Clouard
STMicroelectronics, France
The trend of the smaller the better in semiconductor industry pictures a bright future for System-on-Chip (SoC). The full exploitation of new silicon capabilities, however, is limited by the tremendous SoC design complexity to be addressed within very short project schedule. This limiting factor has pushed the need for altering the classic SoC design flow into prominence. A novel SoC design flow starting from a higher abstraction level than RTL, i.e. System-to-RTL design flow, has surfaced as a real need in advanced SoC design teams. After a decade of attempts to define a useful intermediate abstraction between SoC paper specification and synthesizable RTL, the SystemC C++ open-source class library has finally emerged as the right vehicle to explore the adequate level of abstraction. Transaction Level Modeling (TLM), a methodology based upon such abstraction, has proven revolutionary values in bringing software and hardware teams together using the unique reference model; resulting in dramatic reduction of time-to-market and improvement of SoC design quality.
system-on-chip; integrated circuit; SoC bottleneck; system-to-RTL design flow; transaction level modeling; TLM; abstraction level; SystemC; OSCI.
An electronic system is a blend of hardware and software components intended for performing a set of functions. These functions have to be delivered to target users at a satisfactory level of performance.
The integrated circuit (IC) or chip is a semiconductor wafer comprising millions of interconnected transistors as well as passive components such as resistors...
