ABSTRACT

Functional verification has traditionally focused on providing tools to generate tests and measuring their so-called coverage. The need to provide the correct reference data has had however relatively little attention. This chapter describes how to apply TLM models as executable functional specifications to generate the compulsory reference data required by functional verification environments. We further explain how these models can be used in conjunction with other verification techniques such as hardware emulators, and how formal verification techniques can be applied to TLM models.

KEY WORDS

verification; IP test bench; system test bench; test scenario; input data; test stimuli; expected value; golden reference; data manager; signal-transaction conversion; pin convertor; signal convertor; bus functional model; monitor; checker; transactional co-emulation; formal verification; LusSy; Lustre.

1. INTRODUCTION

The functional verification of a SoC design is a phase that guarantees the compliance of the design implementation with its specification. It is a complex and time-consuming design step, accomplished by converting the specifications into a combination of:

1. Stimuli and expected results scenarios, verifying that the design produces the expected results when applied with the stimuli.

2. Golden model and stimuli constraints, verifying that, whatever the constraint-compliant stimuli, the golden model and RTL behavior are equivalent.

3. Properties and stimuli constraints, verifying that, whatever the constraint-compliant stimuli, the properties hold true.

Using TLM for performing...