5.1 In this Chapter

This chapter continues the presentation of the serial communication interfaces with the description of the I2C bus. It contains suggestions about a possible software implementation of the I2C protocol, and examples on how to connect a 24 256 I2C memory to a microcontroller.

5.2 The Principles of Implementation of the I2C Bus

An I2C bus (Inter IC bus) consists of two signal conductors named SDA (Serial Data) and SCL (Serial Clock) that interconnect at least two devices. Each of the devices connected to the bus must be identified by a unique address. In principle, any of the devices connected to the bus can transmit and receive data. The device that initiates and completes a bus transfer, and generates the transfer clock, is named the MASTER.

As any of the devices connected on the bus can become MASTER at a certain time, the SDA and SCL lines must both be bi-directional. In practice open drain or open collector lines are used. The pull-up resistors have usual values between 2 K and 10 K, depending on the chosen communication speed (at high speed, the pull-up resistor has a smaller value). The idle status of the SDA and SCL lines is HIGH. A bus transfer sequence comprises the following steps:

1. The MASTER device generates a START condition on the bus.

2. The MASTER device generates eight SCL pulses controlling the SDA line in such a way that it transmits a byte which contains the SLAVE's device address and codes...