TABLE OF CONTENTS Chapter 3 presented the overall power consumption sources in a digital microprocessors and, in particular, the four parameters on which a designer can operate to reduce the power consumption: voltage, physical capacitance, switching activity and frequency (see Equation 3.8). All the power reduction techniques presented in this chapter represent an attempt to reduce one of these parameters. In the following sections, we briefly analyze the power optimization techniques available at each level of abstraction in the representation of a microprocessor, starting from technology optimizations up to system-level optimizations. Concerning the system-level optimizations, we focus on the state-of-the-art design space exploration methodologies as well as dynamic power management techniques since they are of fundamental importance in the context of this work.
Several optimizations can be performed directly on the technological parameters as well as on physical-level description without modifying other high-level characteristics of the system. As can be seen from Equation 3.8, a clock frequency decrease causes a proportional decrease in the power dissipation. However, this approach is not viable for high-performance digital systems, where the clock frequency is one of the primary design targets to do not violate peak-performance throughput constraints. In fact, reducing the clock frequency results in a slower computation, the power consumption over a given period of time is reduced, but the total amount of work per unit of time reduced as well. In other words, the energy dissipated to complete the given task does not change. Under the assumption that the total amount...
