List of Tables

Chapter 4: Instruction-Level Power Estimation for VLIW Processor Cores

Table 4.1: VLIW operation classes considered for the target VLIW processor
Table 4.2: Characterization results for the matrix ? summed over the pipeline stages for all pairs of operations when neither pipeline stalls nor I-cache misses occur. Energy values are given in [pJ].
Table 4.3: Comparison results of measured vs. estimated power values for each pipeline stage and for the interconnection.

Table 6.1: Comparison between IL power estimates and RTL power estimates for the benchmark set for the core processor
Table 6.2: Comparison between IL and RTL power estimates for the benchmark set for the Register File
Table 6.3: Refill behavior of the I-cache
Table 6.4: Behavior of the D-cache
Table 6.5: Comparison between Instruction-Level power estimates and RTL power estimates for the benchmark set for the caches

Table 9.1: The set of benchmarks used for the sensitivity analysis.
Table 9.2: The set of optimal parameters and sensitivity indexes for the chosen set of reference applications.
Table 9.3: The set of benchmarks used for the validation of the sensitivity approach
Table 9.4: Comparison between the full search optimal configurations ( a _opt) and the configurations obtained with the sensitivity optimizer ( _opt).
Table 9.5: The set of benchmarks used for the sensitivity analysis.
Table 9.6: The set of optimal parameters and sensitivity indexes for the chosen set of reference applications.
Table 9.7:...

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