This chapter presents a more general power optimization technique, aiming at optimizing the system architecture in terms of memory hierarchy with respect to the applications intended for the embedded system. It consists of a system-level design methodology for the efficient exploration of the architectural parameters of the memory sub-systems, from the energy-delay joint perspective. The aim is to find the best configuration of the memory hierarchy without performing the exhaustive analysis of the parameters space. The target system architecture includes the processor, separate instruction and data caches, the main memory, and the system buses. To achieve a fast convergence toward the near-optimal configuration, the proposed methodology adopts an iterative local-search algorithm based on the sensitivity analysis of the cost function with respect to the tuning parameters of the memory sub-system architecture. The exploration strategy is based on the Energy-Delay Product (EDP) metric taking into consideration both performance and energy constraints. The effectiveness of the proposed methodology will be shown through the design space exploration of two real-world case studies: the optimization of the memory hierarchy for an Lx-based system and a MicroSPARC2-based system, both executing the set of Mediabench benchmarks for multimedia applications. Experimental results show an average optimization speedup of 2 orders of magnitude with respect to the full search approach, while achieving either the same optimal solution obtained by the exhaustive system-level exploration or a sub-optimal configuration characterized, in average, by a distance from the optimal full search configuration in the range of 16%.