List of Figures

Chapter 2: Microprocessor Abstraction Levels

Figure 2.1: Possible abstraction levels for the description of microprocessor based embedded systems
Figure 2.2: Example of a gate-level description of a circuit in Verilog
Figure 2.3: RT-level description in Verilog of the circuit of Figure 2.2

Figure 3.1: A CMOS inverter
Figure 3.2: A rising output transition on the CMOS inverter
Figure 3.3: A falling output transition on the inverter
Figure 3.4: A static CMOS NAND gate
Figure 3.5: Short-circuit current generated during a transition of a CMOS inverter
Figure 3.6: Logic circuit without reconvergent fanout
Figure 3.7: Logic circuit with reconvergent fanout
Figure 3.8: Gate-level power estimation flow
Figure 3.9: A power state machine for a disk drive

Figure 4.1: Traditional (a) and pipeline-aware (b) instruction-level energy models
Figure 4.2: Comparison between traditional and pipeline-aware instruction-level energy models.
Figure 4.3: Architecture of the target VLIW pipelined core
Figure 4.4: A trace of execution showing two data cache misses and two instruction cache misses
Figure 4.5: The system-level test-bench used to validate the model.
Figure 4.6: Agreement between measured and estimated power values when neither I-cache misses nor D-cache misses occur. (Absolute maximum error 11.4%).
Figure 4.7: Agreement between measured and estimated power values when D-cache misses occur. (Absolute maximum error 20.2%).
Figure 4.8: Agreement between measured and estimated power values when I-cache misses occur. (Absolute maximum error 9.6%).
Figure 4.9: Comparison between measured and estimated power values for the given set...

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