Estimation of power consumption in an architecture envisioned for low-power applications is, fairly often, the first step towards power-oriented design optimization. We present now a low-power approach to the design of embedded VLIW processor architectures that exploits the "forwarding" (also called "bypassing") hardware already existing in the Data Path and providing operands from inter-stage pipeline registers directly to the inputs of the function units. This hardware is here used for avoiding the power cost of writing/reading short-lived variables to/from the Register File (RF). In many embedded systems applications, a significant number of variables are short-lived, that is their liveness (from first definition to last use) spans only few instructions. Values of short-lived variables can then be accessed directly through the forwarding registers, avoiding write-back to the RF by the producer instruction, and successive read from the RF by the consumer instruction. The compiler (through its static scheduling algorithm) decides on enabling the RF write-back phase. Our approach implies a minimal overhead on the complexity of the processor's control logic and no significant increase in length of the critical path.

Application of the proposed solution to a VLIW embedded core, when accessing the Register File, has shown a power saving up to 26.1% with respect to the unoptimized approach on a set of target benchmarks. We conclude this chapter outlining possible extensions of the proposed approach that introduce a new level on the memory hierarchy, consisting of the pipeline microregisters level. This extensions virtually increase RF space and, thus, reduce the...