Overview

The semiconductor market is characterized by an increasing demand for low power system-on-a-chip solutions imposing new challenges mainly related to the management of the complexity, and the support for the specification, design, analysis and validation phases.

Given the complexity of envisioned systems, the ideal approach could be to involve the designer in architectural space exploration and high-level optimization, while synthesis (hardware and software) would be best carried out by CAD tools. Such a solution would exploit the best characteristics of human designers namely, creativity and flexibility and of automatic tools, i.e., efficiency and accuracy.

Given the ever-increasing importance of power as a design constraint, satisfactory architecture-space exploration can be carried out only if fast and accurate tools for power estimation and optimization are available already at the higher abstraction levels.

The main contribution of this thesis is the introduction of innovative power estimation and optimization methodologies to support the design of low power embedded systems based on high-performance VLIW microprocessors.

The proposed power estimation techinques address the instruction-level as well as the system-level power consumption of VLIW-based architectures. Such techniques allow a fast and accurate power estimation framework by reducing the characterization complexity proper of all instruction level models that take into account inter-instruction effects. The proposed techniques have been used to estimate the power consumption of an industrial VLIW architecture by providing a significant speed-up of the estimation process and a reasonable accuracy.

The proposed power optimization techniques address the microarchitectural-level as well as the system-level. Two main optimization techniques...