In this Appendix, experimental results concerning measurements on some integrated current conveyors will be presented. In particular, we have considered five of the presented topologies, fabricated in a 0.35 ?m CMOS technology, provided by Austria Mikro Systems. The circuits have been designed without particular requirements, except for what concerns the X node parasitic impedance. That's why the results found in the previous chapters cannot be used for a comparison and new simulations using Spectre have been performed.

The first fabricated CCII topology is reported again in figure B.1, while in figure B.2 the microphotograph of the chip is presented.

Figure B.1: First CCII topology fabricated

Figure B.2: Microphotograph of figure B.1 topology

First of all, the bandwidth of the current conveyor has been evaluated. A sinusoidal signal having an amplitude of 100 mV has been applied to the Y node, while X node has been left unloaded. The. frequency of the signal has been varied and the corresponding signal amplitude at X node has been measured.

The results concerning the frequency response have been summarised in the graph shown in figure B.3.

Figure B.3: Measured frequency response of figure B.1 topology

The frequency response shows, in the experimental measures, a peak at about 1 MHz which did not result from simulations. Another interesting parameter is represented by the dynamic range, which has evaluated applying a constant voltage to Y node and measuring the corresponding voltage at X node. In other words, we have performed a group of measurements very...