TABLE OF CONTENTS In this chapter, some circuit solutions and a design example for the implementation of low-voltage low-power (LV LP) CCIIs in CMOS technology will be investigated. The behaviour of the topologies presented in the previous chapter will be analysed at reduced supply voltages and new LV LP topologies will be also presented. An analysis of two important parameters in LV LP applications, offset and noise, will conclude the chapter.
Recently, integrated circuit designers have been putting an increasing effort into the reduction of supply voltage and power dissipation of digital, analog and mixed circuits and systems. This is mainly due to the following factors. First of all, the need to reduce power consumption in modern high-density digital systems. As chip components get closer together, the problem of heat dissipation increases while break-down voltages of the components on chip reduce as geometries become smaller. Secondly, the explosive growth of the market of portable battery-operated electronics, which has stimulated the demand for LP topologies able to operate at reduced supplies and to ensure a longer battery lifetime. In this sense, LV LP techniques are mandatory for implantable devices, such as pace-makers, blood flow-meters, hearing instruments, and auditory stimulators, and for portable radios and PCs, cellular phones, pagers, etc. Thirdly, LP solutions are spreading into fields like filters, audio signal processing, EMC compliant systems, etc, where non-invasive sensors can be integrated on-chip. Lastly, there is a huge scientific interest in exploring the technological and...
