Last revised: November 5, 2024
Reviewed by: Scott Orlosky consulting engineer

An IC PCI (Peripheral Component Interconnect) bridge is an electronic device or chip that connects a device with a particular PCI protocol to another PCI type, or to another device with a different protocol. It can also be used as a hub to expand the number of PCI slots available in a PCI system.

Operation

Modern computer peripherals, such as monitors, storage, and printers, require high speed interconnections and seamless equipment exchange. In 1993, engineers at Intel Architecture Development Lab innovated a protocol called peripheral component interconnect.

There is a PCI bus common to all PCI-based peripherals connected to the bus. Data from each device transmits at 32 bits per second for standard PCI. In order for the host (CPU) to receive data from only one of the connected devices, the PCI protocol contains features that allow the bus to decide which peripheral gains access to the host. For a standard PCI system, no more than five devices can be connected in order to minimize interference.  Reference Figure 1, below for an example block diagram showing how multiple PCI devices can be connected.

Figure 1: Example system with a PCI bridge connected to the main bus and managing
a secondary bus with connected devices.
Image credit: A. Michelin/GlobalSpec

Advantages

Speed and Bandwidth

The standard, basic PCI protocol transfers data at a rate of 32 bits per second, at a maximum clock speed of 33 MHz, so the bandwidth is 132 megabytes per second.

Hot Swap

The protocol enables the replacement of system devices without needing to turn off the system. This reduces the mean time to repair (MTTR), an important factor in contemporary computer networks.

Configurability

PCI is a "smart" protocol. If new devices are added to the system, then the PCI protocol configures the new layout automatically, without human intervention.

Types

There are several modalities of PCI protocol. Some of the most important are as follows.

PCI

This was the original standard protocol with a typical speed of 32 bps and maximum bandwidth of 132 MB per second, as defined earlier.

PCI-X (PCI eXtended) version 1.0

A PCI variety that operates at a speed of 64 bps and clock speeds of 66 MHz and 133 MHz. This combination produces bandwidths of 528 MB/s and 1064 MB/s respectively.

PCI-X (PCI eXtended) version 2.0

This is PCI-X version with clock rates of 266 MHz and 533 MHz, which can produce bandwidths of 2.128 GB/s and 4.264 GB/s, respectively.

PCI Express (PCIe)

PCI express (PCIe) fits common system architectures, provides greater speed and independence, and increases bandwidth and scalability. PCIe offers 4 Gbps of peak bandwidth per direction and 8 Gbps of concurrent bandwidth. PCIe is referred to as a third-generation input/output (3GIO). 

The table, below, provides a quick summary of the variations that have evolved over time with the PCI concept. The current incarnation with the PCI-E version has become the standard due to its ability to move data more quickly in a much reduced form factor — making it easier to incorporate in hardware.

Specifications

• Protocols: PCI, PCI-X, or PCIe
• Data rate: Rate of data transmission and reception, in bites per second (bps or b/s)
• PCI data bus: 32-bit or 64-bit
• GPIO port: the number of general purpose ports that can be connected to the bridge
• Power dissipation: power dissipated by the device during operation

IC PCI Bridges FAQs

What is the role of the Host-to-PCI bridge?

The Host-to-PCI bridge plays a crucial role in system design by facilitating communication between the local processor bus and the PCI bus. Here are some detailed insights into its role:

The Host-to-PCI bridge translates signals and data between the local processor bus and the PCI bus. This is necessary because modern processors do not have a PCI bus directly connected to the chip. Instead, they use a local bus optimized for the specific processor architecture.

In conventional PC environments, the Host-to-PCI bridge is often referred to as the "North Bridge." It is a component of the chipset that manages main memory and the Level 2 cache. This integration helps streamline data flow and control between the processor and other system components.

The architecture of the Host-to-PCI bridge is designed to mimic the PCI-to-PCI (P2P) bridge specification as much as possible. This design choice helps maintain consistency and compatibility within the PCI architecture.

Some local buses supported by the Host-to-PCI bridge can accommodate multiple processors, enhancing the system's ability to handle parallel processing tasks and improving overall performance.

These roles highlight the importance of the Host-to-PCI bridge in ensuring efficient communication and data handling between the processor and the PCI bus, which is essential for the smooth operation of modern computing systems.

How does the Host-to-PCI bridge compare to other types of PCI bridges?

The Host-to-PCI bridge plays a distinct role compared to other types of PCI bridges, such as PCI-to-PCI (P2P) bridges and PCI-to-Legacy Bus bridges.

Functionality: It translates signals and data between the local processor bus and the PCI bus. This is necessary because modern processors do not have a PCI bus directly connected to the chip; instead, they use a local bus optimized for the specific processor architecture.

Integration: Often referred to as the "North Bridge" in conventional PC environments, it is part of the chipset that manages main memory and the Level 2 cache. This integration helps streamline data flow and control between the processor and other system components.

Architecture: Its architecture mimics the PCI-to-PCI (P2P) bridge specification to maintain consistency and compatibility within the PCI architecture.

Functionality: Connects two PCI bus segments, primarily used to overcome electrical limitations and to allow portions of the system to operate in parallel.

Specification: Defined in the PCI-to-PCI Bridge Architecture Specification, it serves to extend the PCI bus by adding more devices or segments.

Functionality: Typically connects PCI to older bus architectures like ISA, although specific details are not provided in the documents.

In summary, the Host-to-PCI bridge is essential for translating and managing data flow between the processor and the PCI bus, while the PCI-to-PCI bridge extends the PCI bus capabilities by connecting multiple segments. The PCI-to-Legacy Bus bridge serves to connect PCI with older bus systems.

What are the benefits of using PCI Express over traditional PCI?

Here are the benefits of using PCI Express (PCIe) over traditional PCI:

PCI Express offers significantly higher bandwidth compared to traditional PCI. It provides dedicated bandwidth to each device, unlike PCI, which shares bandwidth among devices. For example, a PCI Express x1 link provides 250 MB/s, a x4 link provides 1 GB/s, and a x16 link provides 4 GB/s of dedicated bandwidth.

PCI Express uses a serial, point-to-point interface, which eliminates the need for devices to arbitrate for bus control. This architecture allows for more efficient data transfer and reduces latency compared to the parallel, multi-drop interface of traditional PCI.

The layered architecture of PCI Express allows for scalability to higher bandwidths without compromising software compatibility. Future speed upgrades can be achieved by changing the Physical Layer while maintaining the Data Link Layer and Transaction Layer.

PCI Express maintains software backward compatibility with PCI, allowing users to preserve their software investments when transitioning to PCI Express.

PCI Express simplifies I/O operations and improves serviceability and scalability due to its layered architecture. This makes it suitable for a wide range of applications, from desktop PCs to enterprise servers and communication switches.

These benefits make PCI Express a preferred choice over traditional PCI in many modern computing and communication applications.

What are some details about the layered architecture of PCI Express?

The layered architecture of PCI Express (PCIe) is a key feature that contributes to its performance, scalability, and compatibility.

PCI Express is a serial, point-to-point interface, which differs from the parallel, multi-drop interface of traditional PCI. This architecture allows for more efficient data transfer and reduces latency.

Transaction Layer: This is the topmost layer responsible for creating and managing transactions. It handles the types of information that can be exchanged and the methods for doing so.

Data Link Layer: This layer ensures reliable data transfer between two directly connected devices. It manages error detection and correction, ensuring data integrity.

Physical Layer: The bottom layer deals with the actual transmission of data across the physical medium. It is responsible for the electrical and mechanical aspects of the PCIe interface.

Scalability: The layered architecture allows for future scalability to higher bandwidths without compromising software compatibility. For example, speed upgrades can be achieved by changing the Physical Layer while maintaining the Data Link Layer and Transaction Layer.

Serviceability and Extensibility: The architecture simplifies I/O operations and improves serviceability, making PCIe suitable for a wide range of applications from desktop PCs to enterprise servers.

These layers work together to provide a robust and flexible framework for data communication in PCI Express systems, enabling high performance and adaptability to evolving technological needs.

How does PCI Express maintain backward compatibility with PCI?

PCI Express maintains backward compatibility with PCI primarily through its software compatibility. Here are some key points.

PCI Express is designed to be backward compatible with the PCI software infrastructure. This means that users transitioning to PCI Express can preserve their existing software investments without needing significant changes to their software systems.

The layered architecture of PCI Express allows for future scalability to higher bandwidths without compromising software compatibility. This is achieved by making changes at the Physical Layer while maintaining the Data Link Layer and Transaction Layer, ensuring that the software interface remains consistent.

These aspects ensure that while PCI Express offers advanced features and higher performance, it still supports the existing software ecosystem built around PCI, facilitating a smoother transition for users upgrading their systems.

What is the role of each layer?

The layered architecture of PCI Express (PCIe) is designed to enhance performance, scalability, and compatibility. Here is a detailed explanation of the role of each layer:

Transaction Layer

Role: This is the topmost layer responsible for creating and managing transactions. It handles the types of information that can be exchanged and the methods for doing so.

Functionality: The Transaction Layer is involved in the generation of requests and responses, managing the flow of data packets between devices. It ensures that data is correctly formatted and routed to the appropriate destination.

Data Link Layer

Role: This layer ensures reliable data transfer between two directly connected devices.

Functionality: It manages error detection and correction, ensuring data integrity. The Data Link Layer is responsible for establishing and maintaining a reliable link between devices, handling acknowledgments, and retransmissions if necessary.

Physical Layer

Role: The bottom layer deals with the actual transmission of data across the physical medium.

Functionality: It is responsible for the electrical and mechanical aspects of the PCIe interface. This includes the encoding and decoding of data, as well as the physical transmission of signals over the PCIe lanes.

These layers work together to provide a robust and flexible framework for data communication in PCI Express systems, enabling high performance and adaptability to evolving technological needs.

IC PCI Bridges Media Gallery

References

GlobalSpec—Introduction to PCI Express: A Hardware and Software Developer's Guide

GlobalSpec—PCI Bus Demystified, Second Edition

Images credits:

Wikimedia