TABLE OF CONTENTS The notion of bridging plays a significant role in PCI architecture primarily due to electrical limitations that impose a severe limit on the number of devices residing on a single PCI bus segment. In some cases, it is also desirable to functionally isolate portions of the system so they can operate in parallel.
In this chapter, we're primarily concerned with the PCI-to-PCI (P2P) bridge, that is, a bridge that connects two PCI bus segments. The P2P bridge is defined in PCI-toPCI Bridge Architecture Specification, Rev. 1.1, December 1998. But before delving into the details of the P2P bridge, we should note briefly that there are two other types of bridges that serve specific roles as illustrated in Figure 7-1.
None of today's popular processor architectures has a PCI bus coming directly off the chip. Rather, each processor defines its own local bus optimized around the specific architecture. External cache and main memory often reside on the local processor bus. Some local busses also support multiple processors.
The Host-to-PCI bridge provides the translation from the local processor bus to the PCI. In conventional PC environments, the Host-to-PCI bridge, often referred to as the "North Bridge," is one element of the chipset and is usually contained in the same chip that manages main memory and the Level 2 cache. To the extent feasible, the architecture of the Host-to-PCI bridge mimics the P2P bridge specification.
Someday, the ISA bus will...
