TABLE OF CONTENTS We conclude our tour of the world of PCI with a look at the electrical and mechanical aspects of PCI-X.
PCI-X Mode 2 introduces a new signaling environment that operates at 1.5 volts. To clarify the characteristics and requirements of the various signaling environments, PCI-X categorizes all bus signals as shown in Table 14-1.
| Category | Supply Voltage | Output Type | Input Terminator | Signals | |
|---|---|---|---|---|---|
| 1 | Model 1 | 3.3V | Totem Pole | No | AD C/BE# PAR64/ECC[7] REQ64#/ECC[6] ECC[5::2] ACK64#/ECC[1] PAR/ECC[0] |
| Model 2 | 1.5V | Totem Pole | Yes | ||
| 2 | 3.3V | Totem Pole | No | FRAME# DEVSEL# IRDY# TRDY# STOP# IDSEL PERR# LOCK# REQ# GNT# CLK RST# | |
| 3 | 3.3V | Open Drain | No | SERR# INTx# | |
| 4 | See PCI 3.0 | M66EN PRSNT[1::2]#TCKTDI TDO TMS TRST#SMBCLK SMBDAT | |||
| 5 | See PCI PM 1.1 | PME# | |||
| 6 | n/a | PCIXCAP MODE2 |
The nature of these signals depends on which PCI-X mode the device is operating in. In Mode 1, they use 3.3V signaling and common clock timing for the entire transaction. In Mode 2, they use 1.5V signaling and source synchronous timing for data phases. Other phases of a transaction use common clock timing.
The 1.5V signaling environment uses a differential receiver with an input termina' tion resistor.
These basic control signals always operate at 3.3V and use common clock timing.
These are the open drain signals. SERR# is asserted synchronously with the clock but its deassertion is asynchronous. Both edges of INTx# are asynchronous to the clock.
