Perhaps the most significant new feature in Version 2.0 is the notion of Source Synchronous Burst Push transactions. Up to this point in the book, everything we've talked about is synchronized by the clock signal. PCI-X 2.0 refers to this as common clock sampling. One obvious consequence of common clock sampling is that there is exactly one data transfer per clock cycle. At 133 MHz and 64 bits, that amounts to roughly one Gbyte/sec transfer rate. The way PCI-X gets to 2 Gbytes and 4 Gbytes is by introducing multiple data subphases within each clock cycle as illustrated in Figure 12-9. PCI-X 266 has two data subphases per clock cycle while PCI-X 533 has four.

Figure 12-9: Source synchronous burst write.

Source synchronous transfers apply only to burst-push transactions, i.e., burst writes, where the initiator generates strobe signals used by the target to clock the data subphases. All other transactions in Mode 2, as well as the Address and Attribute phases of burst-push transactions, use common-clock sampling. During a source synchronous transfer, the C/BE# signals are reassigned as pairs of strobes during data phases (see Table 12-4). FSTROBE (first strobe) and SSTROBE (second strobe) are 180 degrees out of phase such that the first data subphase is clocked by the rising edge of FSTROBE and the second subphase is clocked by the rising edge of SSTROBE.