Recognizing that PCI-X may be useful in embedded applications where size and cost are significant considerations, PCI-X 2.0 defines a 16-bit interface. There are a number of conditions and restrictions on the 16-bit interface:

• It only operates in Mode 2. Mode 2 devices are required to support the 16-bit bus.

• Devices designed exclusively for 16-bit embedded applications need not implement features that aren't required for Mode 2 operations such as parity generation. Category 1 signals on these devices need not support 3.3V signaling

• Bridges are not permitted to connect a 16-bit bus to a subordinate bus. Stated another way, bridges do not support the 16-bit bus on the primary or upstream side.

• Bus width is 16 bits only. There is no dynamic bus width negotiation protocol.

• As the 16-bit interface is optimized for embedded applications, no add-in card connector is specified and no status bit in Configuration Space defines this characteristic. Beyond the basic protocol, much of the 16-bit interface is implementation-defined.

In addition to the normal bus control signals, 16-bit PCI-X uses:

• AD[31::16]

• C/BE#[3::2]

• ECC[5::2]

The protocol is quite simple. Everything that occurs in a single phase on a 32-bit bus requires two subphases or clock cycles on the 16-bit bus. The low-order 16 data bits and two low-order C/BE# bits are transferred in the first subphase, and the high-order bits are transferred in the second subphase. The 16-bit bus uses the same 7-bit ECC algorithm as the 32-bit bus with an additional bit for improved...