TABLE OF CONTENTS The previous chapter described the basic data transfer protocol, the process of moving data from one place on the bus to another. PCI incorporates a number of optional and advanced features that substantially extend its capabilities.
The PCI specification considers interrupt support "optional." There are four interrupt lines, INTA# to INTD#, defined on the PCI connector. However, a single-function device can only use INTA#. Multifunction devices can use any combination of the four interrupt signals. A single-function device is a component or add-in board that embodies exactly one logical device or function. A multifunction device may incorporate anywhere from two to eight logical functions. Each function has its own PCI configuration space. In all cases, the interrupt connection is encoded in the read-only Interrupt Pin register of the function's configuration space. Each function may only be connected to a single interrupt line.
PCI interrupts are defined as level-sensitive, assertion-low [1] and asynchronous with respect to the PCI clock. A device requests attention from its device driver by asserting (driving low) its INTx# signal. The interrupt signal remains asserted until the device driver clears the condition that caused the interrupt. The device then deasserts its INTx#.
Note that the INTx# signals are not necessarily bussed. They are open-drain, so they could be and in fact often are. The specification allows complete freedom in the matter of how interrupt sources are connected to the interrupt controller. But as in many similar...
