PCI Bus Demystified, Second Edition

PCI-X constitutes an extensive set of enhancements to the basic PCI protocol. These include:
Revised command protocol emphasizing a distinction between DWORD and burst transactions.
An Attribute phase in each transaction to identify the initiator of the transaction.
Split transactions whereby a request is completely decoupled from the response. PCI-X Split Transactions replace conventional PCI's Retry.
An error correction protocol that allows single bit errors to be corrected automatically.
Source synchronous data transfers that yield up to 4 Gbytes of bandwidth. Source synchronous transfers implement either two or four data subphases per clock cycle.
Device ID Messaging that allows a device to talk directly to another device outside of the normal bus address spaces. The target of such a transaction may be explicitly specified by bus, device and function number or implicitly as the host bridge.
A 16-bit interface optimized for embedded applications.
The next chapter looks at configuration and initialization issues in PCI-X.