TABLE OF CONTENTS Since the PCI Bus accommodates multiple masters any of which could request the use of the bus at any time there must be a mechanism that allocates use of bus resources in a reasonable way and resolves conflicts among multiple masters wishing to use the bus simultaneously. Fundamentally, this is called bus arbitration.
Before a bus master can execute a PCI transaction, it must request, and be granted, use of the bus. For this purpose, each bus master has a pair of REQ# and GNT# signals connecting it directly to a central arbiter as shown in Figure 2-1. When a master wishes to use the bus, it asserts its REQ# signal. Sometime later the arbiter will assert the corresponding GNT# signal indicating that this master is next in line to use the bus.
Only one GNT# signal can be asserted at any instant in time. The master agent who sees his GNT# asserted may initiate a bus transaction when it detects that the bus is idle. The bus idle state is defined as both FRAME# and IRDY# deasserted.
Figure 2-2 is a timing diagram illustrating how arbitration works when two masters request use of the bus simultaneously.
The arbiter detects that device A has asserted its REQ#. No one else is asserting a REQ# at the moment so the arbiter asserts GNT#-A. In the meantime, device B asserts its REQ#
