TABLE OF CONTENTS The protocol enhancements described up until now were originally defined in Version 1.0 of the PCI-X Addendum. Devices that only support these features of PCI-X are said to operate in Mode 1. The remainder of this chapter describes protocol enhancements subsequently introduced in Version 2.0 of the Addendum. Devices that support these additional features are said to operate in Mode 2.
All PCI-X devices are required to generate and check parity in essentially the same manner as conventional PCI. To briefly summarize the parity requirements:
Even parity is computed across the AD and C/BE# busses and driven on PAR (AD[31 ::0] and C/BE[3::0]) and PAR64 (AD[63::32] and C/BE[7::4] for 64-bit devices) by the device that drives the AD bus.
PAR and PAR64 are valid one clock cycle after the cycle for which parity is computed.
The device checking parity does so in the clock cycle after the cycle in which PAR and PAR64 are valid.
A device that detects a parity error in the Address or Attribute phases of a transaction asserts SERR# two clock cycles after PAR and PAR64 are valid and sets the Detected Parity Error bit in its Status Register.
A device that detects a parity error for a data phase asserts PERR# (if enabled) two clock cycles after PAR and PAR64 are valid.
PCI-X Version 2.0 introduced...
