TABLE OF CONTENTS The essence of any bus is the set of rules by which data moves between devices. This set of rules is called a "protocol." This chapter describes the basic protocol that controls the transfer of data between devices on a PCI bus.
The PCI bus command for a transaction is conveyed on the C/BE# lines during the address phase. Note that when C/BE# is carrying command data it is assertion high (high level = logic 1), whereas when it carries byte enable data it is assertion low.
The PCI bus defines three distinct address spaces with corresponding read and write commands as shown in Table 3-1. The principal distinction between memory and I/O spaces is that memory is generally considered to be "prefetchable," meaning that reads from memory space have no "side effects." In contrast, a read from I/O space may have the side effect of, for example, resetting the Data Ready bit in a status register. If such a register were prefetched but not actually read, data could be lost.
| C/BE#3 | C/BE#2 | C/BE#1 | C/BE#0 | Command Type |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | Interrupt Acknowledge |
| 0 | 0 | 0 | 1 | Special Cycle |
| 0 | 0 | 1 | 0 | I/O Read |
| 0 | 0 | 1 | 1 | I/O Write |
| 0 | 1 | 0 | 0 | Reserved |
| 0 | 1 | 0 | 1 | Reserved |
| 0 | 1 | 1 | 0 | Memory Read |
| 0 | 1 | 1 | 1 | Memory Write |
| 1 | 0 | 0 | 0 | Reserved |
| 1 | 0 | 0 | 1 | Reserved |
| 1 | 0 | 1 | 0 | Configuration Read |
| 1 |
