TABLE OF CONTENTS Figures 12-1 and 12-2 illustrate respectively a typical PCI write transaction and the corresponding PCI-X transaction. Let's first review the PCI write transaction.
| 1 | The bus is idle and most signals are tri-stated. The initiator for the upcoming transaction has received GNT# and asserts FRAME#. It also places the target address on the AD bus and the bus command on the C/BE bus. |
| 2 | Address Phase. All targets detect the beginning of a transaction and sample the address on the AD bus and the command on the C/BE bus. One target recognizes that it has been selected. |
| 3 | The initiator may now place write data on the AD bus and assert the correspending byte enables on the C/BE bus along with IRDY#. |
| 4 | The target requires an extra clock to respond by asserting DEVSEL# and TRDY#. In this case both IRDY# and TRDY# remain asserted for the entire transaction resulting in four data phases in four contiguous clocks. |
| 7 | The initiator negates FRAME# signifying that this is the last data phase. The initiator must leave IRDY# asserted for at least one clock cycle beyond the negation of FRAME# to guarantee the turnaround cycle between transactions. |
| 8 | The target negates DEVSEL# and TRDY#. The initiator negates IRDY#. This is the turnaround cycle that guarantees... |
