TABLE OF CONTENTS Table 12-2 lists PCI-X commands along with the corresponding PCI command for the same C/BE encoding. As in PCI, initiators must not generate commands identified as "Reserved," and targets must not respond to them by asserting DEVSEL#.
| Encoding | PCI Command | PCI-X Command | Length | Byte Enable Usage | Notes [1] |
|---|---|---|---|---|---|
| 0000b | Interrupt Acknowledge | Interrupt Acknowledge | DWORD | attr | |
| 0001b | Special Cycle | Special Cycle | DWORD | attr | |
| 0010b | I/O Read | I/O Read | DWORD | attr | |
| 0011b | I/O Write | I/O Write | DWORD | attr | |
| 0100b | Reserved | Reserved | N/A | N/A | |
| 0101b | Reserved | Device ID Message | Burst | none | |
| 0110b | Memory Read | Memory Read DWORD | DWORD | attr | |
| 0111b | Memory Write | Memory Write | Burst | data phase | |
| 1000b | Reserved | Alias to Memory Read Block | Burst | none | [2] |
| 1001b | Reserved | Alias to Memory Write Block | Burst | none | [3] |
| 1010b | Configuration Read | Configuration Read | DWORD | attr | [4] |
| 1011b | Configuration Write | Configuration Write | DWORD | attr | [4] |
| 1100b | Memory Read Multiple | Split Completion | Burst | none | |
| 1101b | Dual Address Cycle | Dual Address Cycle | N/A | N/A | [1] |
| 1110b | Memory Read Line | Memory Read Block | Burst | none | |
| 1111b | Memory Write and Invalidate | Memory Write Block | Burst | none | |
| [1]For all commands except Dual Address Cycle, the command appears on C/BE[3:0]# during the address phase. For transactions with dual address cycles, C/BE[3:0]# contains the Dual Address Command during the first address cycle and the transaction command during the second address cycle. For 64-bit transactions, C/BE[7:4]# contain the... |
