TABLE OF CONTENTS The PCI-X protocol has a number of implications for configuration transactions and how a system is initialized.
In most PCI implementations, a device's IDSEL signal is connected to one of the upper AD lines on the backplane. To minimize DC loading on the AD line, the connection is made through a series resistor. The downside is that the capacitive load of the IDSEL input must be charged through this resistor and that takes a finite time. With PCI-X running at 133 MHz, it can take more than one clock for IDSEL to be recognized as asserted.
PCI-X deals with this by requiring that the initiator of a configuration transaction assert the address on the AD bus four clocks before asserting FRAME#. This is illustrated in Figure 13-1.
The initiator is allowed to assert the address on the AD bus as soon as it recognizes its GNT# signal asserted. However, until it asserts FRAME# four clocks later, the bus is technically idle. Meanwhile, the arbiter may remove GNT# in favor of a higher priority device. If that happens, if for example GNT# is removed before clock n, the current initiator must float the AD bus within two clocks of seeing GNT# negated and try again.
Bus segments capable of Mode 2 operation are not allowed to connect IDSEL to an AD line because they use...
