TABLE OF CONTENTS PCI-X is officially considered to be an addendum to the PCI Local Bus Specification [1] . Revision 1.0 was introduced in 1999 to be followed by Revision 2.0 in 2002.
When PCI was first introduced in 1992, its maximum bandwidth of 132 Mbytes per second matched well with the processors and peripherals of the day. Today's faster I/O technologies, such as Gigabit Ethernet, Ultra-3 SCSI and Fibre Channel require higher bandwidth system busses to operate at peak efficiency.
Revision 2.0 of PCI-X supports a maximum bandwidth of over 4 Gbytes per second, enough to provide some "headroom" for a few years anyway. Figure 11-1 compares bandwidths for several popular interconnect mechanisms. PCI-X is the clear leader.
[1]It's a pretty big addendum. Revision 2.0 of the PCI-X protocol is 388 pages, versus 344 pages for Revision 3.0 of the PCI specification. Then there are another 137 pages of electrical and mechanical specifications.
Revision 1.0 PCI-X enhancements fall into two basic categories: higher clock frequency 133 MHz and enhancements to the protocol to make it more efficient for large block transfers. This yields roughly a gigabyte of bandwidth for a 64-bit bus.
The protocol enhancements include:
A split cycle. This is a substitute for the Retry protocol in PCI. A target that can't complete a transfer within the maximum latency notifies the initiator with a Split Completion termination. Later, the target initiates a transaction back to the original initiator...
