20.0 INTRODUCTION

The dominant trend within electronics today is the drive toward increasingly smaller feature sizes on integrated circuit (IC) chips. Ten years ago, feature sizes of 1 m were the norm; by the mid-1990s, 0.35 m was the norm, and research and development ICs are at 0.25 m and under. This has led to a drastic increase in the number of input-outputs (I/Os) on the chip, particularly for application-specific ICs (ASICs). Indeed, 300 to 500 I/Os per chip are no longer uncommon, and now ASICs having up to and higher than 1000 I/Os are under development. Figure 20.1 shows different surface-mount components from plated through-hole (PHT) to chip scale packages (CSPs) in the trend toward miniaturization.

FIGURE 20.1: Electronics package miniaturization trends.

This great increase in I/Os pushes on the packaging engineer to arrive at a suitable way of interconnecting the IC to a printed wiring board (PWB) or to a ceramic substrate. Mounting on an organic substrate, typically referred to as a PWB, is much less expensive than mounting on a ceramic substrate. Concomitant with the increase in I/Os, or pins, is the drive to achieve higher component densities, thereby increasing board functionality. The current trend in electronic packaging is

• Increasing pin count

• Increasing component density (more functionality per unit area)

• Lighter weight

Several different approaches are being employed to meet the challenge of mounting high-pin-count ICs to substrates and packages on PWBs. These approaches can be considered a...