Building the Power-Efficient PC: A Developer's Guide to ACPI Power Management
This book provides developers and integrators with practical knowledge and design techniques for building PCs that address the increasing demand for energy conservation.
TABLE OF CONTENTS Building the Power-Efficient PC: A Developer's Guide to ACPI Power Management
Appendix B: ACPI Registers, Bits, and Control Methods
This appendix defines the specific ACPI registers, bits, and control methods mentioned in the text. See the ACPI 2.0 Specification for definitions of the entire set of ACPI registers, bits, and control methods.
ACPI Registers, Bits, and Values
ACPI_ENABLE
A value written to SMI_CMD which generates an event to the hardware to transition the platform into ACPI mode.
ACPI_ENABLE is specifically the value to write to SMI_CMD to disable SMI ownership of the ACPI hardware registers. The last action SMI takes to relinquish ownership is to set the SCI_EN bit. During the OS initialization process, OSPM synchronously waits for the transfer of SMI ownership to complete, so the ACPI system releases SMI ownership as quickly as possible. This field is reserved and must be zero on systems that do not support Legacy Mode.
GPE0_BLK, GPE1_BLK
The GPE0_BLK and GPE1_BLK blocks provide the foundation for an interrupt-processing model for Control Methods. GPE0_BLK is the system port address of General-Purpose Event 0 Register Block. This is an optional field; if this register block is not supported, this field contains zero. This field is superseded in ACPI 2.0 by the X_GPE0_BLK field.
P_BLK
The P_BLK blocks are for controlling processor features. There is an optional processor control register block for each processor in the system. As this is a homogeneous feature, all processors must have the same level of support. The ACPI OS will revert to the lowest common denominator of processor control block support. The processor control block contains the processor control...
Copyright Intel Corporation 2001 under license agreement with Books24x7
