TABLE OF CONTENTS This chapter examines the design of dividers and PFDs. The main application for dividers is in the feedback path of PLL-based frequency synthesizers, dividing the oscillator output down to the reference frequency. There are several challenges in divider design, which this chapter will discuss. The oscillator drives the divider input and, since this is the highest frequency in the circuit, speed is a big challenge in divider design. At each subsequent stage, the speed is lower, and the challenge becomes to operate at the required speed at the lowest power dissipation. Another challenge is that dividers need to be programmable and, in many cases, adjustable in real time. They may be dynamically switched between two or more different divider ratios to generate the equivalent of a fractional-divider ratio. Such dividers are called dual-modulus or multimodulus dividers. As a related topic to frequency division, the design of frequency multipliers is also discussed briefly.
The phase detector or PFD directly follows the divider. The PFD compares the divided-down signal with the reference signal and provides an error voltage, which is ultimately fed back to control the oscillator. In this chapter, a variety of design issues and challenges will be discussed. This will include techniques to avoid the dead zone, a situation in which the PFD is not able to respond to the phase difference between the divider output and the reference signal. Another topic for discussion is circuitry to detect the lock condition. Finally, some of the differences in design...
