Intel IXA is fully software programmable and uses memory for storing data structures and buffering packet data. Specifically, IXP2XXX network processors use ring buffers and linked lists to pass messages and data between microengines and buffer packets in DRAM. This technique is illustrated in the packet flow example in Chapter 1. Quickly accessing data structures with minimal latency in SRAM (and internal scratch memory) is very critical. When a software application is right in the middle of a complex processing algorithm and needs to access a data structure before processing can continue, memory access needs to be very quick or else processing stalls and packets may get dropped. In Intel IXA, linked lists and ring buffers are used extensively throughout the packet processing cycle. These linked lists and ring buffers are very complex memory operations that involve several read and write operations to manage the data structure. Because they are right in the middle of the processing flow, they need to be turned around very quickly. As such, these operations are fully automated in IXP2XXX network processors to reduce programming burden and minimize memory latency so high line rates can be achieved. The goal of this chapter is to give you a fundamental under- standing how IXP2XXX processors manage linked lists and ring buffers.