Intel Internet Exchange Architecture and Applications: A Practical Guide to IXP2XXX Network Processors

Glossary

3DES
3DES is a more secure standard of DES that runs its algorithm three times with variations on the algorithm. The IXP2850 processor implements this algorithm.
ADT
ADT stands for Architecture Development Tool. Intel developed this tool to help system engineers estimate performance of applications and map tasks to microengines.
AES
AES stands for Advanced Encryption Standard. The National Institute of Standards and Technology (NIST) initiated it to replace DES.
Aggregate_ID
Aggregate_ID is an identifier used in the Pool of Threads (POTs) programming model to group similar packets together. By grouping similar packets together, threads won t block waiting for out-of-order packets from dissimilar flows to arrive at ordered processing nodes (OP nodes).
AISR
AISR stands for Asynchronous Insert, Synchronous Remove, the data structure and mechanism used in the Pool of Threads (POTs) programming model to ensure end-to-end packet ordering.
Atomic Memory Operation
Atomic Memory Operation is a multi-access, Read-Modify-Write (RMW) memory operation in which no other memory accesses are interleaved between the separate memory accesses of the RMW. Atomic memory operations are important when updating critical data so software mechanisms aren t needed to lock the data during updates.
Cached Queue Descriptor
Cached Queue Descriptor is a queue descriptor that is cached in an SRAM Q_Array entry. A queue array qnum identifier is then stored in the MEv2 CAM.
Cbus
Cbus is the CSIX flow control bus used...

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