10.3.1 Genetic Algorithms in Network Synthesis

Digital network synthesis has been developed to a point where most designs can be generated automatically on a computer. A specification written in a hardware description language such as VHDL or Verilog can be compiled into a form suitable for programming a FPGA or fabricating a full custom integrated circuit, with little or no human intervention.

The situation is very different for analogue network synthesis, however. With the exception of the limited number of problems for which formal design solutions exist, there are no automatic design tools available for analogue networks. As a consequence most analogue network design is still performed manually by skilled engineers. Although the analogue part of most electronic systems is often a small part of the overall system, it is usually the most expensive part in terms of design effort. Recently there have been attempts to automate the analogue network design process by the use of Genetic Algorithms (GAs) in conjunction with high-level statements of the desired response.

There is no reason in principle why the network topology and the component values should not be chosen using entirely different methods. Clearly there is a natural hierarchy: the network topology must be determined before the component values can be selected. Nevertheless, these two operations can be performed separately, and different optimization techniques can be used. Specifically, the network topology can be optimized using GAs; for each network topology generated the component values can then be determined by numerical...