10.9.1 Development of a Genetic Algorithm Technique for VLSI Testing

The objective of VLSI testing is to generate compact set of test vectors that has high coverage of manufacturing defects.

• Stuck at fault modeling is the widely used fault modeling method in VLSI Testing.

• Here nodes are assumed to be stuck at either "0" or "1", for the purpose fault modeling.

• Testing methodology for a digital circuit is shown in Fig. 10.44.

  
  Fig. 10.44: Digital circuit

• Test vectors are encoded as Binary bit stream.

• Fitness function gives the number of faults covered by each test vector.

Consider the XOR circuit shown in the Fig. 10.45 below.

Fig. 10.45: XOR circuit

The description of given XOR Circuit is as follows:

• Number of primary inputs is "2" and primary output is "1".

• Each parent width is 2 bits.

• In this example, XOR circuit has 12 fault sites and 24 stuck at faults.

• For a fault free circuit, the output is "1" for a input vector [1,0].

• If the circuit has a stuck at "0" at "a", the output response is "0". So input vector [1,0] detects stuck at 0 [SA0] fault at "a".

• Like wise [1,0] can also detect SA0 fault at [a, c, d, g, h, z] and SA1 at [b, e, j].

• Thus [1,0] can detect 9 out of a total of 24 faults and it's fitness is 0.375 [i.e. 9/24].

The experimental circuit is as given below in Fig. 10.46. Table...