TABLE OF CONTENTS Nowadays, the operating frequency of VCOs designed in CMOS technology can be as high as 50 GHz (Wang, 2001). To be able to track high-frequency output signals from such VCOs, to lock PLLs or synthesizers, it is important to include in the feedback loop CMOS frequency dividers that can operate at the same operation frequencies. On the other hand, after the first few dividers, the signal frequency becomes low enough that it is more power efficient to use other dividers that can operate at a much lower frequency but with much lower power consumption. As such, both divider topologies are generally needed, one of which is for high frequencies but high power consumption, whereas the other is for low frequencies and low power consumption. The following sections will describe different divider implementations for the two categories.
The differential source-coupled logic (SCL) frequency divider is generally recognized as the fastest divider topology and it can be realized by cascading two D-latch stages as shown in Fig. 3.17. Two D-latch stages are cascaded with the output of the second stage cross-coupled to the input of the first stage to perform a divide-by-2 function. Each of the two D-latches consists of a cross-coupled pair (M3, M4) connected in a positive feedback configuration to provide negative transconductance to maximize the operation frequency. Each D-latch is driven by a single clock with two complementary clock phases, one of which is used to...
