Low-Voltage CMOS RF Frequency Synthesizers

3.3. Prescaler

3.3. Prescaler

A prescaler is a combination of several simple dividers and counters to achieve a sophisticated divider with more complicated division ratios. In practice, different divider and prescaler topologies can be combined in order to achieve both the required speed and the total division ratio while minimizing the power consumption. Moreover, depending on the specification and applications, prescalers may be either non-programmable or programmable, the latter of which is required to obtain different division ratios for channel selection.

3.3.1. Non-programmable prescaler

Non-programmable dividers have fixed division ratios and can simply be constructed by cascading several dividers in series as illustrated in Fig. 3.23. After the first-stage divider, the successive dividers are configured as a ripple counter to pass signals through one stage after another. As a result, the operation frequency is the highest for the first divider but becomes lower and lower from stage to stage. The first few dividers can be realized employing either SCL or injection-locked topologies as discussed in Section 3.2 to achieve the desired high operation frequency. The last few dividers operating at lower frequency can be implemented using TSPC or static-logic dividers to minimize their power consumption and complexity.


Fig. 3.23: Example of divide-by-32 using a cascade of several dividers

3.3.2. Dual-modulus prescaler

In order to change the VCO frequency without varying the reference frequency in a synthesizer, the division ratio of the divider in the feedback loop should be changed, which can be accomplished by a...

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