3.4. Phase Frequency Detectors (PFDs)

A phase detector (PD) detects the phase difference at its inputs and generates corresponding up and down outputs to control charge pumps. A PD is normally able to work when two input signals have a very small frequency difference. Once the frequency difference gets large enough, another frequency-locked loop or a phase-frequency detector (PFD) is needed to perform phase and frequency comparisons. In general, a PFD can offer a larger acquisition range than a simple PD.

3.4.1. Phase detector design

There are two main types of phase detector (PD) implementation, one is for analog PD and the other is for digital PD. Analog PDs in general can operate at higher frequencies than digital PDs and can be realized simply using Gilbert cell architecture (Gray and Meyer, 1992), in which the output depends on the phase error of the input signals. However, the gain of these PDs depends on the input signal amplitude, which in turn affects the loop gain of the whole PLL. In addition, the power consumption is relatively high compared to digital PDs. Digital PDs can be implemented with exclusive-OR (XOR) logic gates as illustrated in Fig. 3.31. This architecture is simpler and the gain is independent of the input amplitude. On the other hand, since they are digital circuits, the input signals are required to be rail-to-rail, and the operating speed is therefore slower.

Fig. 3.31: (a) XOR phase detector, (b) timing diagram of (a)