TABLE OF CONTENTS This chapter introduces a dual-loop synthesizer for the GSM 900 specification using the 0.5 m CMOS process with a supply voltage of 2 V. This architecture can show the advantage of providing narrow channel selection but offering low phase noise and fast switching time. The performance of the synthesizer achieves a high operating frequency (935.2 959.8 MHz), low power consumption (34 mW), low phase noise ( ?121.8 dBc/Hz at 600 kHz), low spurious level ( ?82.0 dBc at 11.3 MHz) and fast switching time (830 s).
The performance of frequency synthesizers is mainly specified by their output frequency, phase noise, spurious level and switching time. This section derives the specifications of a frequency synthesizer for GSM receivers.
In GSM 900 systems, the receiver-channel frequencies are expressed as follows:
where N = 1, 2, , 124 is the channel number. To receive signals in different channels, a GSM-receiver front-end shown in Fig. 6.1 is adopted. The receiver front-end consists of a low noise amplifier (LNA) and an RF filter for filtering out-of-band noise and blocking signals. The received signal is then mixed down to an IF frequency ( f IF) of 70 MHz for base-band signal processing. To extract information from the desired channel, the local oscillator (LO) output frequency ( f LO) of the frequency synthesizer is changed accordingly as follows:
which is the output-frequency range of the frequency synthesizer to be achieved.
