TABLE OF CONTENTS Cost of test (COT) is an ever-increasing and important issue among chip vendors. The longer it takes to test a chip, the lower its throughput and the higher its production cost will be. Much of what motivates chip manufacturers and test houses to employ parallel and concurrent testing methods is the attempt to reduce the overall COT (see Chapter 5 for more detail about COTS). One good way of reducing the overall test time or the effective test time is to test chips in parallel. This has a direct positive impact on COT because in theory it increases the throughput as compared with the test time of single-site testing. Most chip vendors employ some sort of parallel testing, especially if the production chip volumes are high or the market life of the production chip is or will be very long [1].
Parallel testing of digital and mixed-signal devices has long been the norm. Digital device testing is naturally conducive to parallel methods, and 16-, 32-, and 64-bit parallel buses have been in existence for decades. If one device is already being tested with a 64-bit parallel bus, then why not test a second, or third, or fourth device in parallel using the same method. Figure 7.1 shows a block diagram of two devices being tested in parallel. Using this simple digital test model, the number of devices that can be tested in parallel is limited only by the number of...
